In a C64 replacing the DRAM with an SRAM is no longer an issue, but so
far there was no working design to do the same in a 264 (C16/116/+4).
I was bored yesterday evening and decided to change that. I still had an
Alliance AS6C1008 (55ns) around and since TED supplies its address lines
unmultiplexed most of the wiring is rather simple:
A0-A15, D0-D7 are connected 1:1.
/OE on the RAM is tied low, CS2 and A16 are tied high.
/CS on the RAM is /CAS from TED.
The only problematic signal was R/W, that one has to be routed through
an inverter and then NAND'ed with PHI0 before being connected to the RAM.
So all you need besides the RAM is a single 74LS00.
My hacked together test circuit has so far survived all software I
tested it with, including some demos. So if you can't find 64Kx4 DRAMs,
you now have an alternative.
While checking why the RAM didn't run with R/W connected directly I
noticed that TED uses a different RAS/CAS timing than VIC. VIC will take
/RAS and /CAS HIGH on the rising or falling edge of PHI0. TED on the
other hand will take both signals HIGH about 100ns _after_ the rising or
falling edge of PHI0. No problem with a read cycle, but on a write
cycle, that'll cause problems.
Message was sent through the cbm-hackers mailing list