Some years ago I saw a photograph of some guys with a board as big as a table
with the comment that they succeeded in copying a Z80 only using normal
TTL-ICs. That triggered me to do some research my self. But until now I am
stuck with one problem: the instruction decoder. My idea about it is a ROM-like
construction with the following inputs:
- 8 bits instruction code
- 4 (or more) bits special inputs like Reset, IRQ, NMI, SO (future: Abort)
- 1 bit instruction/special
- 3 bits countsignal derived from the clock
Total of 13 inputs. You could think of a 2764-EPROM but they have one
Another idea is to use Cache-RAMs, I have some of 15ns. They could be used
during the test phase but on the end we need a permanent solution.
The last thing I am thinking of is to calculate all the equations and build the
decoder completely out of gates and decoders.
So if anyone has an idea, please let me know. BTW, there is one restriction:
for the moment only normal available parts are allowed. So no GALs or PALs for
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Ruud Baltissen wrote:
> Total of 13 inputs. You could think of a 2764-EPROM but they have one
> disadvantage: SLOOOOOOOOOW.
> Another idea is to use Cache-RAMs, I have some of 15ns. They could be used
> during the test phase but on the end we need a permanent solution.
> The last thing I am thinking of is to calculate all the equations and build the
Why not load the SRAMs from an EPROM on powerup - you could easily
change the code and still have the speed of the SRAMs.