Free (as in freedom) FPGA development tools

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Free (as in freedom) FPGA development tools

Marko Mäkelä
I just encountered an interesting piece of news in Planet Debian.

It apparently is now possible to use free (as in freedom or Debian Free
Software Guidelines) software tools to translate VHDL into Lattice
FPGAs:

https://bits.debian.org/2016/12/fpga-programming-debian.html
https://wiki.debian.org/FPGA/Lattice

I look forward to seeing the first use of this for Commodore hardware.  
Perhaps someone could develop a switchless ROM cartridge with this? Or
something fancier, such as a REU clone, if the supported FPGAs are big
enough to accommodate such a design.

(I hope this is not old news. Reverse engineered support for some old
FPGAs has been around quite a while.)

        Marko

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Re: Free (as in freedom) FPGA development tools

silverdr-2

> On 2016-12-22, at 14:21, Marko Mäkelä <[hidden email]> wrote:
>
> I just encountered an interesting piece of news in Planet Debian.
>
> It apparently is now possible to use free (as in freedom or Debian Free Software Guidelines) software tools to translate VHDL into Lattice FPGAs:
>
> https://bits.debian.org/2016/12/fpga-programming-debian.html
> https://wiki.debian.org/FPGA/Lattice
>
> I look forward to seeing the first use of this for Commodore hardware.  Perhaps someone could develop a switchless ROM cartridge with this? Or something fancier, such as a REU clone, if the supported FPGAs are big enough to accommodate such a design.
>
> (I hope this is not old news. Reverse engineered support for some old FPGAs has been around quite a while.)

This is obviously interesting. BTW I am still stuck with my search for working set of free like in speech tools that would allow me to program some SPLDs (CPLDs later). Or any tools that would actually work and let me translate synthesizable VHDL designs into  GAL JEDEC files.

--
SD!


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Re: Free (as in freedom) FPGA development tools

Rainer Buchty
On Thu, 22 Dec 2016, [hidden email] wrote:

> BTW I am still stuck with my search for working set of free like in
> speech tools that would allow me to program some SPLDs (CPLDs later).
> Or any tools that would actually work and let me translate
> synthesizable VHDL designs into GAL JEDEC files.

VHDL for GALs will be hard to find. The former Xilinx Webfitter had a
VHDL frontend that could be used together with a GAL (and CPLD) fitter,
but unfortunately that was discontinued several years ago and AFAIK
never released as download software.

If you find something that creates logic equations from VHDL input, you
could eventually translate them to be fed into PALASM1.5, WinCUPL or
OpalJr which all are freely available these days.

In any case, you will most likely require some sort of translator script
that creates proper PALASM or CUPL from the flattened logic equations
the VHDL synthesizer (hopefully) outputs.

Given the low complexity of S/CPLDs, though, I don't think you'll gain
much there from using VHDL over CUPL. (PALASM is more rudimentary but ok
if you just want to do basic equations, truth tables, or state machines.
Using PALTOGAL.EXE you can convert the JEDEC files from PAL/PALCE to
GAL.)

Rainer


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Re: Free (as in freedom) FPGA development tools

Ingo Korb
In reply to this post by silverdr-2
[hidden email] writes:

> Or any tools that would actually work and let me translate
> synthesizable VHDL designs into GAL JEDEC files.

IIRC Lattice ispLEVER Classic can do that.

-ik

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Re: Free (as in freedom) FPGA development tools

silverdr-2

> On 2016-12-23, at 01:33, Ingo Korb <[hidden email]> wrote:
>
> [hidden email] writes:
>
>> Or any tools that would actually work and let me translate
>> synthesizable VHDL designs into GAL JEDEC files.
>
> IIRC Lattice ispLEVER Classic can do that.

Yes - in theory. In practice it is one of those that don't "actually" work. I already spent some sizeable amount of time trying to find answers why it doesn't do what's expected.

Like here:

https://groups.google.com/d/msg/comp.lang.vhdl/ISVk3-TVpTM/Q6L92vmgDQAJ

It basically outputs:

*******
Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro '


Copyright (c) 1991-2010 Lattice Semiconductor Corporation,  All rights reserved.
Version : 2.0.00.17.20.15

Done sucessfully with exit code 1.
Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2

Done: failed with exit code: 0002.
*******

and so far nobody's been able to tell me why or how to make it not to.

--
SD!


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Re: Free (as in freedom) FPGA development tools

silverdr-2
In reply to this post by Rainer Buchty

> On 2016-12-22, at 23:19, Rainer Buchty <[hidden email]> wrote:
>
> On Thu, 22 Dec 2016, [hidden email] wrote:
>
>> BTW I am still stuck with my search for working set of free like in speech tools that would allow me to program some SPLDs (CPLDs later). Or any tools that would actually work and let me translate synthesizable VHDL designs into GAL JEDEC files.
>
> VHDL for GALs will be hard to find.

Yeah, tell me about it ;-) And even those, which theoretically should be capable of things, are no longer to find. At least from authoritative sources.

> The former Xilinx Webfitter had a VHDL frontend that could be used together with a GAL (and CPLD) fitter, but unfortunately that was discontinued several years ago and AFAIK never released as download software.
>
> If you find something that creates logic equations from VHDL input, you could eventually translate them to be fed into PALASM1.5, WinCUPL or OpalJr which all are freely available these days.
>
> In any case, you will most likely require some sort of translator script that creates proper PALASM or CUPL from the flattened logic equations the VHDL synthesizer (hopefully) outputs.
>
> Given the low complexity of S/CPLDs, though, I don't think you'll gain much there from using VHDL over CUPL.

The reason for insisting on VHDL is that I am trying to build a library of tested "building blocks" that may at some point find their ways into more complex designs. So going the CUPL way for example doesn't serve a longer-term goal.

> (PALASM is more rudimentary but ok if you just want to do basic equations, truth tables, or state machines. Using PALTOGAL.EXE you can convert the JEDEC files from PAL/PALCE to GAL.)

Well, the only way I found but not yet tested is to output for PAL from "Cypress Galaxy WARP" and then use PALTOGAL.EXE. After some struggle I got the copy of the "Cypress Galaxy WARP", which (unlike ispLever) didn't break on my VHDL and was able to output something. I still need to find the PALTOGAL stuff and try if that works somehow.

--
SD!


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Re: Free (as in freedom) FPGA development tools

Didier Derny
In reply to this post by silverdr-2
I use ispLEVER Classic and vhdl to make GALs

till now it worked but I'm doing very basic thing

such as making chip selects


I use Lattice 22V10D




On 23/12/2016 11:31, [hidden email] wrote:

>> On 2016-12-23, at 01:33, Ingo Korb <[hidden email]> wrote:
>>
>> [hidden email] writes:
>>
>>> Or any tools that would actually work and let me translate
>>> synthesizable VHDL designs into GAL JEDEC files.
>> IIRC Lattice ispLEVER Classic can do that.
> Yes - in theory. In practice it is one of those that don't "actually" work. I already spent some sizeable amount of time trying to find answers why it doesn't do what's expected.
>
> Like here:
>
> https://groups.google.com/d/msg/comp.lang.vhdl/ISVk3-TVpTM/Q6L92vmgDQAJ
>
> It basically outputs:
>
> *******
> Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro '
>
>
> Copyright (c) 1991-2010 Lattice Semiconductor Corporation,  All rights reserved.
> Version : 2.0.00.17.20.15
>
> Done sucessfully with exit code 1.
> Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi
> Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2
>
> Done: failed with exit code: 0002.
> *******
>
> and so far nobody's been able to tell me why or how to make it not to.
>


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