Die shot of the 8500R4 CPU

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Die shot of the 8500R4 CPU

Gerrit Heitsch


Anyone wants to compare the 8500 and the 8501? Now you can...

https://siliconpr0n.org/map/mos/8500r4


I would really like to know why they removed port bit 5 from the 8501
while the 8500 has all 8 port bits them.

  Gerrit


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Re: Die shot of the 8500R4 CPU

Segher Boessenkool
On Tue, Dec 27, 2016 at 07:14:47PM +0100, Gerrit Heitsch wrote:
> Anyone wants to compare the 8500 and the 8501? Now you can...
>
> https://siliconpr0n.org/map/mos/8500r4
>
>
> I would really like to know why they removed port bit 5 from the 8501
> while the 8500 has all 8 port bits them.

Because they needed the space for the control circuitry for the GATE pin,
I think.


Segher


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smf
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Re: Die shot of the 8500R4 CPU

smf
In reply to this post by Gerrit Heitsch
The 8500 only has P0-P5 bonded out.

I've not seen an 8501 die shot, but I assumed the 8 bits were all there
and they only bonded out P0-P4 & P6-P7. It had to fit in a 40 pin chip
and they also dropped NMI & Phi2 out.

It would have made more sense if the 6510/8500 bonded out P0-P3 & P6 &
P7, as you could use N & V flags after an LDA for branching based on
P6/P7 without any comparison instruction required.

On 27/12/2016 18:14, Gerrit Heitsch wrote:

>
>
> Anyone wants to compare the 8500 and the 8501? Now you can...
>
> https://siliconpr0n.org/map/mos/8500r4
>
>
> I would really like to know why they removed port bit 5 from the 8501
> while the 8500 has all 8 port bits them.
>
>  Gerrit
>
>
>       Message was sent through the cbm-hackers mailing list


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Re: Die shot of the 8500R4 CPU

Gerrit Heitsch
On 12/28/2016 01:06 PM, smf wrote:
> The 8500 only has P0-P5 bonded out.
>
> I've not seen an 8501 die shot, but I assumed the 8 bits were all there
> and they only bonded out P0-P4 & P6-P7. It had to fit in a 40 pin chip
> and they also dropped NMI & Phi2 out.

For the 8501 die shots go here:

http://visual6502.org/images/pages/MOS_8501_die_shots.html


> It would have made more sense if the 6510/8500 bonded out P0-P3 & P6 &
> P7, as you could use N & V flags after an LDA for branching based on
> P6/P7 without any comparison instruction required.

Yes, and you can see the 2 unused pads for P6 and P7 on the die of the 8500.

  Gerrit



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