6522 VIA inputs

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6522 VIA inputs

silverdr-2
In 1541 bits five and six of the VIA port at $1800 are used to initialise the device id. In the older drives, both respective pins are grounded via bridged trace fields. In the newer there is a DIP switch block. I saw this schematic uncountable number of times, yet only recently it struck me that when the trace bridges are cut the pins are left floating (!). There are no pullups whatsoever. Now the question - is this a documented feature of the VIA that can be safely relied upon? Something like "unconnected pins will always read 1 when configured as inputs". I had a look at the 6522 datasheet and found only "Port B lines represent one standard TTL load in the input mode [...]"

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Re: 6522 VIA inputs

Konrad B
"There are no pullups whatsoever."

Are you 100% sure about this ? Check Rockwell's or UMC's datasheets.
Hint: resistor would have to take a lot of the die space, it's easier
to use a transistor for this purpose.

2017-04-21 11:21 GMT+02:00  <[hidden email]>:
> In 1541 bits five and six of the VIA port at $1800 are used to initialise the device id. In the older drives, both respective pins are grounded via bridged trace fields. In the newer there is a DIP switch block. I saw this schematic uncountable number of times, yet only recently it struck me that when the trace bridges are cut the pins are left floating (!). There are no pullups whatsoever. Now the question - is this a documented feature of the VIA that can be safely relied upon? Something like "unconnected pins will always read 1 when configured as inputs". I had a look at the 6522 datasheet and found only "Port B lines represent one standard TTL load in the input mode [...]"
>
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>
>
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Re: 6522 VIA inputs

silverdr-2
In reply to this post by silverdr-2

> On 2017-04-21, at 11:21, [hidden email] wrote:
>
> In 1541 bits five and six of the VIA port at $1800 are used to initialise the device id. In the older drives, both respective pins are grounded via bridged trace fields. In the newer there is a DIP switch block. I saw this schematic uncountable number of times, yet only recently it struck me that when the trace bridges are cut the pins are left floating (!). There are no pullups whatsoever. Now the question - is this a documented feature of the VIA that can be safely relied upon? Something like "unconnected pins will always read 1 when configured as inputs". I had a look at the 6522 datasheet and found only "Port B lines represent one standard TTL load in the input mode [...]"

Even only deciding to post the question seems to help. I _think_ I found the answer immediately after posting the question... In the datasheet there is a Figure 3. Although it's caption says: "Port B Output Circuit", which originally made me believe that it's only the part used when the pin is configured as output, it also contains a line described as "INPUT DATA". This line seems to be in fact pulled up. I assume this is what makes it reliable - a kind of internal pullup. Would still appreciate corrections if I am missing something here.

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Re: 6522 VIA inputs

silverdr-2
In reply to this post by Konrad B

> On 2017-04-21, at 11:32, Konrad B <[hidden email]> wrote:
>
> "There are no pullups whatsoever."
>
> Are you 100% sure about this?

About 1541 providing no pullups for those lines - yes. As for the VIA internal ones - no, I am not. That's what made me ask.

> Check Rockwell's or UMC's datasheets.
> Hint: resistor would have to take a lot of the die space, it's easier
> to use a transistor for this purpose.

That figure ("Figure 3.") in the Rockwell datasheet ("Figure 2." as well) shows a resistance there. I don't know if this is implemented as an on-die resistor or is it only more like a functional schematic and the actual pullup is realised in another way. And I still assume that this is in fact what I was looking for.

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Re: 6522 VIA inputs

Pasi 'Albert' Ojala
In reply to this post by silverdr-2
On 21.04.2017 12:34, [hidden email] wrote:
> Although it's caption says: "Port B Output Circuit", which originally
> made me believe that it's only the part used when the pin is
> configured as output, it also contains a line described as "INPUT
> DATA". This line seems to be in fact pulled up. I assume this is what
> makes it reliable - a kind of internal pullup. Would still appreciate
> corrections if I am missing something here.
Hi,

CMOS uses push-pull drives, but my impression is that older technologies
use pull-ups with open-collector/open-drain drives. I.e. passive up,
active down.

CMOS can emulate open-drain drive by using an external pull-up resistor
and switching between input (high-impedance) and drive-0 states. I have
used this often to create I2C using regular IO pins.

Microcontrollers often have weak pull-downs or pull-ups. However,
resistors in the MOhm range increase the production testing time due to
the requirement to measure very small currents, which is a reason they
are not always used. (In addition to having a minimal effect in leakage
during low-power modes.)

-Pasi



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Re: 6522 VIA inputs

silverdr-2

> On 2017-04-21, at 11:47, Pasi 'A1bert' Ojala <[hidden email]> wrote:
>
> CMOS uses push-pull drives, but my impression is that older technologies use pull-ups with open-collector/open-drain drives. I.e. passive up, active down.
>
> CMOS can emulate open-drain drive by using an external pull-up resistor and switching between input (high-impedance) and drive-0 states. I have used this often to create I2C using regular IO pins.
>
> Microcontrollers often have weak pull-downs or pull-ups. However, resistors in the MOhm range increase the production testing time due to the requirement to measure very small currents, which is a reason they are not always used. (In addition to having a minimal effect in leakage during low-power modes.)

Pasi, thanks - that's the very reason I am looking closer at it! I want to output data to VIA port pins acting as inputs and started to wonder whether I should drive the lines HI (seems to work in tests but if the lines are in fact pulled up then it's presumably unneeded/undesirable) or rather tri-state my outputs instead.

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Re: 6522 VIA inputs

Pasi 'Albert' Ojala
You can probably use a multimeter to measure the resistance from the pin
to GND and to VDD to support or disprove the hypothesis.

Using the diode measurement (to GND and VDD) you could also probably
find protection diodes.

It's of course possible the output driver is push-pull, but has
sufficient leakage for it to float high when in high-impedance (input) mode.


On 21.04.2017 13:11, [hidden email] wrote:
>> On 2017-04-21, at 11:47, Pasi 'A1bert' Ojala <[hidden email]> wrote:
>>
>> CMOS uses push-pull drives, but my impression is that older technologies use pull-ups with open-collector/open-drain drives. I.e. passive up, active down.
>>
>> CMOS can emulate open-drain drive by using an external pull-up resistor and switching between input (high-impedance) and drive-0 states. I have used this often to create I2C using regular IO pins.
>>
>> Microcontrollers often have weak pull-downs or pull-ups. However, resistors in the MOhm range increase the production testing time due to the requirement to measure very small currents, which is a reason they are not always used. (In addition to having a minimal effect in leakage during low-power modes.)
> Pasi, thanks - that's the very reason I am looking closer at it! I want to output data to VIA port pins acting as inputs and started to wonder whether I should drive the lines HI (seems to work in tests but if the lines are in fact pulled up then it's presumably unneeded/undesirable) or rather tri-state my outputs instead.
>


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Re: 6522 VIA inputs

smf
In reply to this post by silverdr-2
On 21/04/2017 11:11, [hidden email] wrote:
> I want to output data to VIA port pins acting as inputs and started to
> wonder whether I should drive the lines HI (seems to work in tests but
> if the lines are in fact pulled up then it's presumably
> unneeded/undesirable) or rather tri-state my outputs instead.

Do whatever is easiest. The pull ups are rather weak & while they work
when you disconnect an input, running a long wire that is tri stated
into the chip is probably not a good idea. It's perfectly acceptable to
ignore the pull ups and drive 0v/5v.



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Re: 6522 VIA inputs

Gerrit Heitsch
In reply to this post by silverdr-2
On 04/21/2017 11:21 AM, [hidden email] wrote:
> In 1541 bits five and six of the VIA port at $1800 are used to initialise the device id. In the older drives, both respective pins are grounded via bridged trace fields. In the newer there is a DIP switch block. I saw this schematic uncountable number of times, yet only recently it struck me that when the trace bridges are cut the pins are left floating (!). There are no pullups whatsoever. Now the question - is this a documented feature of the VIA that can be safely relied upon? Something like "unconnected pins will always read 1 when configured as inputs". I had a look at the 6522 datasheet and found only "Port B lines represent one standard TTL load in the input mode [...]"
>

Take a look at the MOS datasheet for the 6522 (If you can't find it, I
can mail it to you), it has schematics for the port drivers for port A
and port B, they differ, but both ports have a permanent pullup in form
of a MOS transistor for each bit.

  Gerrit





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Re: 6522 VIA inputs

Mike Naberezny
On 4/21/17 9:10 AM, Gerrit Heitsch wrote:
> Take a look at the MOS datasheet for the 6522 (If you can't find it, I can
> mail it to you), it has schematics for the port drivers for port A and port B,
> they differ, but both ports have a permanent pullup in form of a MOS
> transistor for each bit.

The MOS 6522 datasheet can be downloaded from here:
http://6502.org/documents/datasheets/mos/

The port drivers are on page 3 of the PDF.  The Rockwell and Synertek 6522
datasheets are also on 6502.org.

Regards,
Mike

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Re: 6522 VIA inputs

silverdr-2

> On 2017-04-21, at 19:12, Mike Naberezny <[hidden email]> wrote:
>
>> Take a look at the MOS datasheet for the 6522 (If you can't find it, I can mail it to you), it has schematics for the port drivers for port A and port B, they differ, but both ports have a permanent pullup in form of a MOS transistor for each bit.

Yeah - thanks. I had only the Rockwell's one at hand with a somewhat misleading caption but it shows more or less the same, except that it shows a resistor instead of transistor. A cursory glance, together with the caption made me initially believe it to be only the output part and a kind of a final output stage inverter. The MOS and Synertek documents seem to be more accurate, even if their captions also talk about output only. I even downloaded the half-gig heavy MOS blueprint scan of the 6522 and it agrees with the MOS datasheet.

> The MOS 6522 datasheet can be downloaded from here:
> http://6502.org/documents/datasheets/mos/
>
> The port drivers are on page 3 of the PDF.  The Rockwell and Synertek 6522 datasheets are also on 6502.org.

Got those, thanks.

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Re: 6522 VIA inputs

silverdr-2
In reply to this post by smf

> On 21/04/2017 11:11, [hidden email] wrote:
>
>> I want to output data to VIA port pins acting as inputs and started to wonder whether I should drive the lines HI (seems to work in tests but if the lines are in fact pulled up then it's presumably unneeded/undesirable) or rather tri-state my outputs instead.
>
> On 2017-04-21, at 15:48, smf <[hidden email]> wrote:
>
> Do whatever is easiest.

The easiest is driving the lines, because I already do it and it seems to work but changing it from driving into tri-stating is not much of work.

> The pull ups are rather weak & while they work when you disconnect an input, running a long wire that is tri stated into the chip is probably not a good idea.

I don't expect the wires to be long enough to have tangible influence but right, I see what you mean.

> It's perfectly acceptable to ignore the pull ups and drive 0v/5v.

I am not sure if I am not trying to overengineer but what causes my doubts is that it's never 0V/5V, and especially never the same between different families of devices, etc.  While pushing the (pulled-up) line LO is OK because that's what it is meant to be done, the potential of the sourcing output and the pulled-up line are almost certainly different so it will have to cause some (unnecessary / unnecessarily higher) current flow through the line, possibly adding to consumption, unwanted emissions, etc. ... or are all those possible side-effects fully negligible and I am just too paranoid here? ;-)

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Re: 6522 VIA inputs

Groepaz
On Friday 21 April 2017, 21:40:17 [hidden email] wrote:

> > It's perfectly acceptable to ignore the pull ups and drive 0v/5v.
>
> I am not sure if I am not trying to overengineer but what causes my doubts
> is that it's never 0V/5V, and especially never the same between different
> families of devices, etc.  While pushing the (pulled-up) line LO is OK
> because that's what it is meant to be done, the potential of the sourcing
> output and the pulled-up line are almost certainly different so it will
> have to cause some (unnecessary / unnecessarily higher) current flow
> through the line, possibly adding to consumption, unwanted emissions, etc.
> ... or are all those possible side-effects fully negligible and I am just
> too paranoid here? ;-)

driving a NMOS i/o line high is a big nono. just dont. its a common thing to
do to connect several outputs together, forming a wired OR - when one of those
outputs is driving high, the one trying to pull low will have a hard time
doing it. even if it still may work, the signal timing will go poop

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Re: 6522 VIA inputs

Gerrit Heitsch
On 04/22/2017 04:35 PM, [hidden email] wrote:

> On Friday 21 April 2017, 21:40:17 [hidden email] wrote:
>>> It's perfectly acceptable to ignore the pull ups and drive 0v/5v.
>>
>> I am not sure if I am not trying to overengineer but what causes my doubts
>> is that it's never 0V/5V, and especially never the same between different
>> families of devices, etc.  While pushing the (pulled-up) line LO is OK
>> because that's what it is meant to be done, the potential of the sourcing
>> output and the pulled-up line are almost certainly different so it will
>> have to cause some (unnecessary / unnecessarily higher) current flow
>> through the line, possibly adding to consumption, unwanted emissions, etc.
>> ... or are all those possible side-effects fully negligible and I am just
>> too paranoid here? ;-)
>
> driving a NMOS i/o line high is a big nono. just dont. its a common thing to
> do to connect several outputs together, forming a wired OR - when one of those
> outputs is driving high, the one trying to pull low will have a hard time
> doing it. even if it still may work, the signal timing will go poop
>

Eh? So far I though NMOS is very good at sinking current to GND, but not
at supplying current from Vcc. Looking at the datasheet for the 6526
supports this, the output driver can supply at most 1mA, but can sink
something in the range of 3mA.

So if you connect 2 NMOS outputs together, the one pulling the line LOW
will win. Also, on most NMOS outputs, you cannot disable the 'pullups'
(see output driver schematic for the 6522).

What you must not do is using a CMOS output set to HIGH and connect it
to an NMOS output set to LOW.

  Gerrit








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Re: 6522 VIA inputs

Groepaz
On Saturday 22 April 2017, 17:12:10 Gerrit Heitsch <[hidden email]>
wrote:

> On 04/22/2017 04:35 PM, [hidden email] wrote:
> > On Friday 21 April 2017, 21:40:17 [hidden email] wrote:
> >>> It's perfectly acceptable to ignore the pull ups and drive 0v/5v.
> >>
> >> I am not sure if I am not trying to overengineer but what causes my
> >> doubts
> >> is that it's never 0V/5V, and especially never the same between different
> >> families of devices, etc.  While pushing the (pulled-up) line LO is OK
> >> because that's what it is meant to be done, the potential of the sourcing
> >> output and the pulled-up line are almost certainly different so it will
> >> have to cause some (unnecessary / unnecessarily higher) current flow
> >> through the line, possibly adding to consumption, unwanted emissions,
> >> etc.
> >> ... or are all those possible side-effects fully negligible and I am just
> >> too paranoid here? ;-)
> >
> > driving a NMOS i/o line high is a big nono. just dont. its a common thing
> > to do to connect several outputs together, forming a wired OR - when one
> > of those outputs is driving high, the one trying to pull low will have a
> > hard time doing it. even if it still may work, the signal timing will go
> > poop
> Eh? So far I though NMOS is very good at sinking current to GND, but not
> at supplying current from Vcc. Looking at the datasheet for the 6526
> supports this, the output driver can supply at most 1mA, but can sink
> something in the range of 3mA.
>
> So if you connect 2 NMOS outputs together, the one pulling the line LOW
> will win. Also, on most NMOS outputs, you cannot disable the 'pullups'
> (see output driver schematic for the 6522).
>
> What you must not do is using a CMOS output set to HIGH and connect it
> to an NMOS output set to LOW.

thats what i ment with "driving high". a NMOS output does never "drive high",
it only ever pulls low.

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Re: 6522 VIA inputs

silverdr-2

> On 2017-04-22, at 17:19, [hidden email] wrote:

>>> driving a NMOS i/o line high is a big nono. just dont. its a common thing
>>> to do to connect several outputs together, forming a wired OR - when one
>>> of those outputs is driving high, the one trying to pull low will have a
>>> hard time doing it. even if it still may work, the signal timing will go
>>> poop

Well, in this particular case it is me who controls what gets connected where. Therefore such an "OR gate" is not going to be a problem. Although...

>> Eh? So far I though NMOS is very good at sinking current to GND, but not
>> at supplying current from Vcc. Looking at the datasheet for the 6526
>> supports this, the output driver can supply at most 1mA, but can sink
>> something in the range of 3mA.
>>
>> So if you connect 2 NMOS outputs together, the one pulling the line LOW
>> will win. Also, on most NMOS outputs, you cannot disable the 'pullups'
>> (see output driver schematic for the 6522).
>>
>> What you must not do is using a CMOS output set to HIGH and connect it
>> to an NMOS output set to LOW.

..., while I am not planning to have this kind of configuration, I can not exclude that e. g. a software bug accidentally configures the pins in such way.

> thats what i ment with "driving high". a NMOS output does never "drive high",
> it only ever pulls low.

So in any case I take the safest/most "correct" way would be to just tri-state my outputs, while - in order to avoid potential issues with longer lines/wires - adding somewhat stronger (say 33k?) pull-ups on my own?

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Re: 6522 VIA inputs

Gerrit Heitsch
In reply to this post by Groepaz
On 04/22/2017 05:19 PM, [hidden email] wrote:

> On Saturday 22 April 2017, 17:12:10 Gerrit Heitsch <[hidden email]>
> wrote:
>> On 04/22/2017 04:35 PM, [hidden email] wrote:
>>> On Friday 21 April 2017, 21:40:17 [hidden email] wrote:
>>>>> It's perfectly acceptable to ignore the pull ups and drive 0v/5v.
>>>>
>>>> I am not sure if I am not trying to overengineer but what causes my
>>>> doubts
>>>> is that it's never 0V/5V, and especially never the same between different
>>>> families of devices, etc.  While pushing the (pulled-up) line LO is OK
>>>> because that's what it is meant to be done, the potential of the sourcing
>>>> output and the pulled-up line are almost certainly different so it will
>>>> have to cause some (unnecessary / unnecessarily higher) current flow
>>>> through the line, possibly adding to consumption, unwanted emissions,
>>>> etc.
>>>> ... or are all those possible side-effects fully negligible and I am just
>>>> too paranoid here? ;-)
>>>
>>> driving a NMOS i/o line high is a big nono. just dont. its a common thing
>>> to do to connect several outputs together, forming a wired OR - when one
>>> of those outputs is driving high, the one trying to pull low will have a
>>> hard time doing it. even if it still may work, the signal timing will go
>>> poop
>> Eh? So far I though NMOS is very good at sinking current to GND, but not
>> at supplying current from Vcc. Looking at the datasheet for the 6526
>> supports this, the output driver can supply at most 1mA, but can sink
>> something in the range of 3mA.
>>
>> So if you connect 2 NMOS outputs together, the one pulling the line LOW
>> will win. Also, on most NMOS outputs, you cannot disable the 'pullups'
>> (see output driver schematic for the 6522).
>>
>> What you must not do is using a CMOS output set to HIGH and connect it
>> to an NMOS output set to LOW.
>
> thats what i ment with "driving high". a NMOS output does never "drive high",
> it only ever pulls low.

The output driver for the B ports on the 6522 disagree.

  Gerrit



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Re: 6522 VIA inputs

smf
In reply to this post by Gerrit Heitsch


On 22/04/2017 16:12, Gerrit Heitsch wrote:
> What you must not do is using a CMOS output set to HIGH and connect it
> to an NMOS output set to LOW.

Do you mean if you have a CMOS and an NMOS connected to each other and
both are set to output then will it break? Or do you mean if you have a
CMOS output set to HIGH and an NMOS output set to LOW connected to a
third input that it will cause a problem?


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Re: 6522 VIA inputs

Gerrit Heitsch
On 04/22/2017 10:10 PM, smf wrote:
>
>
> On 22/04/2017 16:12, Gerrit Heitsch wrote:
>> What you must not do is using a CMOS output set to HIGH and connect it
>> to an NMOS output set to LOW.
>
> Do you mean if you have a CMOS and an NMOS connected to each other and
> both are set to output then will it break?

You might overload the NMOS driver if the CMOS driver can supply more
current than the NMOS driver can sink. Over time that could cause damage.



  Gerrit



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Re: 6522 VIA inputs

smf
On 22/04/2017 21:45, Gerrit Heitsch wrote:
> You might overload the NMOS driver if the CMOS driver can supply more
> current than the NMOS driver can sink. Over time that could cause damage.

So it would depend on the CMOS output current? Would a current limiting
resistor help?


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